1. Field of the Invention
The present invention relates to a junction field effect transistor (so-called J-FET) which can operate at high speed and the manufacturing method thereof.
2. Description of the Prior Art
The efficiency of the junction field effect transistor (J-FET) is roughly expressed by gm/Cg where gm is the mutual conductance and Cg the gate capacitance. The conventional J-FET will hereinafter be described with reference to FIG. 1.
Referring to FIG. 1, the J-FET comprises on a substrate 5 a source region 1, a drain region 2, a gate region 3 and a channel region 4. There are provided a source electrode S, a gate electrode G and a drain electrode D. In this case, ##EQU1## where z is the gate width, L the gate length, Ks.sub..epsilon. 0 the dielectric constant, W the thickness of the depletion layer, q the charge, N the impurity concentration, .phi.B the built-in voltage, Vg the gate voltage, gm.degree. the intrinsic transconductance, GO the channel conductance, d the effective thickness of the channel and .mu. the mobility. Therefore, in order to increase gm/Cg, the gate length L must be decreased as much as possible. Since the source resistance Rs lowers the effective mutual conductance gm, the source resistance Rs must be decreased. If the gate length L is decreased, the short-channel effect occurs so that when the gate is closed, a current flows through the substrate 5 just below the channel region 4. Thus, since the gate is not closed satisfactorily, the impurity concentration N must be increased and the effective thickness d of the channel must be decreased.
By the way, there can be a limit that the gate length L is decreased by the photo-lithography technique. If the electron beam lithography technique and X-ray lithography technique are utilized effectively, the gate length L can be decreased to 1/4 .mu.m. In this case, the J-FET, however, causes a problem. That is, since the gate region 3 is formed in the standard J-FET by the diffusion of impurities, the gate length L becomes longer than that of the lithography rule by diffusing the impurities in the lateral direction. Therefore, even if the gate window of 1/4 .mu.m long can be formed, the effective gate length becomes about 1/3 to 1/2 .mu.m. When the J-FET having a gate length in sub-micron units is formed by the diffusion method, the side capacity C1 of the P.sup.+ gate region 3 is made significant for the intrinsic capacity C2 (.varies.1/L) by the diffusion of the P.sup.+ gate region 3 so that the linear improvement of the efficiency cannot be expected by the decrease of the gate length L.